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ADM1027
Table XII. Register 0x43  VID Register (Power-On Default = 0x00 )
Bit
Name
R/W
Description
<4:0>
VID[4:0]
Read-Only
The VID[4:0] inputs from the CPU to indicate the expected processor core voltage. On
power-up, these bits reflect the state of the VID pins, even if monitoring is not enabled.
<7:5>
Reserved
Read-Only
Reserved for future use.
Table XIII. Voltage Limit Registers
Register Address
R/W
Description
Power-On Default
0x44
Read/Write
2.5 V Low Limit
0x00
0x45
Read/Write
2.5 V High Limit
0xFF
0x46
Read/Write
V
CCP
 Low Limit
0x00
0x47
Read/Write
V
CCP
 High Limit
0xFF
0x48
Read/Write
V
CC
 Low Limit
0x00
0x49
Read/Write
V
CC
 High Limit
0xFF
0x4A
Read/Write
5 V Low Limit
0x00
0x4B
Read/Write
5 V High Limit
0xFF
0x4C
Read/Write
12 V Low Limit
0x00
0x4D
Read/Write
12 V High Limit
0xFF
Setting the Configuration Register 1 lock bit has no effect on these registers.
High Limits: An interrupt is generated when a value exceeds its high limit ( > comparison).
Low Limits: An interrupt is generated when a value is equal to or below its low limit ( ?comparison).
Table XIV. Temperature Limit Registers
Register Address
R/W
Description
Power-On Default
0x4E
Read/Write
Remote 1 Temperature Low Limit
0x81
0x4F
Read/Write
Remote 1 Temperature High Limit
0x7F
0x50
Read/Write
Local Temperature Low Limit
0x81
0x51
Read/Write
Local Temperature High Limit
0x7F
0x52
Read/Write
Remote 2 Temperature Low Limit
0x81
0x53
Read/Write
Remote 2 Temperature High Limit
0x7F
Exceeding any of these temperature limits by 1
o
C will cause the appropriate status bit to be set in the interrupt status register. Setting
the Configuration Register 1 lock bit has no effect on these registers.
High Limits: An interrupt is generated when a value exceeds its high limit ( > comparison).
Low Limits: An interrupt is generated when a value is equal to or below its low limit (?comparison).
Rev. 3 | Page 45 of 56 | www.onsemi.com
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